Universal gates in VHDL

Universal gates in VHDL

NOT GATE – BEHAVIOURAL

library ieee;
use ieee.std_logic_1164.all;
  entity NOT1 is
   port (A : in bit;
        Y: out bit);
  end entity NOT1;
  architecture NOT_1 of NOT1 is
   begin
    process(A)
     begin
      if A='1' then
      Y<='0';
      else Y<='1';
      end if;
      end process;
  end architecture NOT_1;

NOT GATE – DATA FLOW

library ieee;
use ieee.std_logic_1164.all;
  entity NOT1 is
   port (A : in bit;
         Y: out bit);
 end entity NOT1;
 architecture NOT_1 of NOT1 is
  begin
   Y <= NOT A;
 end architecture NOT_1;

AND GATE - BEHAVIOURAL

library ieee;
use ieee.std_logic_1164.all;
  entity AND2 is
   port (A,B : in bit;
         Y: out bit);
  end entity AND2;
  architecture AND_2 of AND2 is
   begin
    process(A,B)
     begin
      if (A='1' and B='1') then
      Y<='1';
      else
      Y<='0';
      end if;
      end process;
  end architecture AND_2;

AND GATE – DATA FLOW

library ieee;
use ieee.std_logic_1164.all;
  entity AND2 is
   port (A,B : in bit;
         Y: out bit);
  end entity AND2;
  architecture AND_2 of AND2 is
   begin
    Y <= A AND B;
  end architecture AND_2;

OR GATE - BEHAVIOURAL

library ieee;
use ieee.std_logic_1164.all;
  entity OR2 is
   port (A,B : in bit;
         Y: out bit);
  end entity OR2;
  architecture OR_2 of OR2 is
   begin
    process(A,B)
     begin
      if (A='0'and B='0') then
      Y<='0';
      else
      Y<='1';
      end if;
    end process;
  end architecture OR_2;

OR GATE – DATA FLOW

library ieee;
use ieee.std_logic_1164.all;
  entity OR2 is
   port (A,B : in bit;
         Y: out bit);
  end entity OR2;
  architecture OR_2 of OR2 is
   begin
    Y <= A OR B;
  end architecture OR_2;

NAND GATE - BEHAVIOURAL

library ieee;
use ieee.std_logic_1164.all;
  entity NAND2 is
   port (A,B : in bit;
         Y: out bit);
  end entity NAND2;
  architecture NAND_2 of NAND2 is
   begin
    process(A,B)
     begin
      if (A='0'or B='0') then
      Y<='1';
      else
      Y<='0';
      end if;
    end process;
  end architecture NAND_2;

NAND GATE – DATA FLOW

library ieee;
use ieee.std_logic_1164.all;
  entity NAND2 is
   port (A,B : in bit;
         Y: out bit);
  end entity NAND2;
  architecture NAND_2 of NAND2 is
   begin
    Y <= A NAND B;
  end architecture NAND_2;

NOR GATE- BEHAVIOURAL


library ieee;
use ieee.std_logic_1164.all;
  entity NOR2 is
   port (A,B : in bit;
         Y: out bit);
  end entity NOR2;
  architecture NOR_2 of NOR2 is
   begin
    process(A,B)
     begin
      if (A='0'and B='0') then
      Y<='1';
      else
      Y<='0';
      end if;
    end process;
  end architecture NOR_2;


NOR GATE – DATA FLOW
library ieee;
use ieee.std_logic_1164.all;
  entity NOR2 is
   port (A,B : in bit;
         Y: out bit);
  end entity NOR2;
  architecture NOR_2 of NOR2 is
   begin
    Y <= A NOR B;
  end architecture NOR_2;

XOR GATE - BEHAVIOURAL

library ieee;
use ieee.std_logic_1164.all;
  entity XOR2 is
   port (A,B : in bit;
         Y: out bit);
  end entity XOR2;
  architecture XOR_2 of XOR2 is
   begin
    process(A,B)
     begin
      if A=B then
      Y <='0';
      else Y<='1' ;
      end if;
    end process;
  end architecture XOR_2;

XOR GATE – DATA FLOW

library ieee;
use ieee.std_logic_1164.all;
  entity XOR2 is
   port (A,B : in bit;
         Y: out bit);
  end entity XOR2;
  architecture XOR_2 of XOR2 is
   begin
    Y <= A XOR B;
  end architecture XOR_2;

XNOR GATE – BEHAVIOURAL

library ieee;
use ieee.std_logic_1164.all;
  entity XNOR2 is
   port (A,B : in bit;
        Y: out bit);
  end entity XNOR2;
  architecture XNOR_2 of XNOR2 is
   begin
    process(A,B)
     begin
      if A=B then
      Y <='1';
      else Y<='0' ;
      end if;
    end process;
  end architecture XNOR_2;