SR-Flipflop

SR-Flipflop

SR-Flipflop(Behavioural Model)

library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
 entity SR_FlipFlop is
  port( S :in std_logic;
        R :in std_logic;
        CLK : in std_logic;
        Q : out std_logic;
        Q1 : out std_logic);
 end SR_FlipFlop;
architecture SR_FF of SR_FlipFlop is
 begin
  process(CLK)
   variable tmp: std_logic;
    begin
     if(CLK='1') then
     if(S='0' and R='0')then
     tmp:=tmp;
     elsif(S='1' and R='1')then
     tmp:='Z';
     elsif(S='0' and R='1')then
     tmp:='0';
     else
     tmp:='1';
     end if;
     end if;
     Q <= tmp;
     Q1 <= not tmp; --Q1 REFERS TO Q'(Q BAR)--
  end process;
end architecture SR_FF;