Multiplexer in VHDL

Multiplexer in VHDL

2-INPUT MUX ( DATA FLOW)

library ieee;
use ieee.std_logic_1164.all;
  entity MUX2 is
   port(D0 : in std_logic;
    D1 : in std_logic;
    S : in std_logic;
    Z : out std_logic);
  end entity MUX2;
  architecture MUX_2 of MUX2 is
   begin
    Z<=(D0 AND (NOT S)) OR (D1 AND S);
  end architecture MUX_2;

4-INPUT MUX (DATA FLOW)

library ieee;
use ieee.std_logic_1164.all;
  entity MUX4 is
   port(D0 : in std_logic;
    D1 : in std_logic;
    D2 : in std_logic;
    D3 : in std_logic;
    S0 : in std_logic;
    S1 : in std_logic;
    Z : out std_logic);
  end entity MUX4;
  architecture MUX_4 of MUX4 is
   begin
    Z<=((NOT S0) AND (NOT S1) AND D0) OR ( S0 AND (NOT S1)AND D1) OR (S0 AND S1 AND D3);
  end architecture MUX_4;