Half Subtractor

Half Subtractor

HALF SUBTRACTOR – DATA FLOW


library ieee;
use ieee.std_logic_1164.all;
  entity HS is
    port(X,Y : in std_logic;
     D,B : out std_logic);
  end HS;
  architecture H_S of HS is
   begin
    D <= X XOR Y;
    B <= (NOT X) AND Y;
  end H_S;


HALF SUBTRACTOR – BEHAVIOURAL

library ieee;
use ieee.std_logic_1164.all;
   entity HS is
     port (X, Y : in std_logic;
           Dif, Bout : out std_logic);
   end entity HS;
   architecture H_S of HS is
    begin
     process(X,Y)
     begin
       if(X='0' and Y='0') then
       Dif <='0';
       Bout <='0';
       elsif(X='0' and Y='1') then
       Dif <='1';
       Bout<='1';
       elsif(X='1' and Y='0') then
       Dif <='1';
       Bout<='0';
       else
       Dif <='0';
       Bout<='0';
       end if;
     end process;
   end architecture H_S;