Full Adder

Full Adder

FULL ADDER – DATA FLOW


library ieee;
 use ieee.std_logic_1164.all;
    entity FA is
     port(A,B,C : in std_logic;
     Sum,Carry : out std_logic);
    end FA;
architecture F_A of FA is
 begin
  Carry<=(A AND B) OR (A AND C) OR (B AND C);
  Sum<=A XOR B XOR C;
 end F_A;


FULL ADDER – BEHAVIORAL

library ieee;
 use ieee.std_logic_1164.all;
  entity FA is
 port (A, B, Cin : in std_logic;
  Sum, Carry : out std_logic);
  end entity FA;
   architecture F_A of FA is
    begin
     process(A,B,Cin)
     begin
      if(A='0'and B='0' and Cin='0') then
      Sum<='0';
      Carry<='0';
      elsif(A='0' and B='0' and Cin='1') then
      Sum<='1';
      Carry<='0';
      elsif(A='0' and B='1' and Cin='0') then
      Sum<='1';
      Carry<='0';
      elsif(A='0' and B='1' and Cin='1') then
      Sum<='0';
      Carry<='1';
      elsif(A='1' and B='0' and Cin='0') then
      Sum<='1';
      Carry<='0';
      elsif(A='1' and B='0' and Cin='1') then
      Sum<='0';
      Carry<='1';
      elsif(A='1' and B='1' and Cin='0') then
      Sum<='0';
      Carry<='1';
      else
      Sum<='1';
      Carry<='1';
      end if;
     end process;
   end architecture F_A;