Encoder in VHDL

Encoder in VHDL

4:2LINE ENCODER (DATA FLOW)

library ieee;
use ieee.std_logic_1164.all;
  entity MUX4_2 is
   port(I0 : in std_logic;
    I1 : in std_logic;
    I2 : in std_logic;
    I3 : in std_logic;
    O1 : out std_logic;
    O2 : out std_logic);
  end entity MUX4_2;
  architecture MUX_4_2 of MUX4_2 is
   begin
    O1<=((NOT I0) AND I1 AND (NOT I2) AND (NOT I3)) OR ((NOT I0) AND (NOT I1) AND (NOT I2) AND (NOT I3));
    O2<=((NOT I0) AND (NOT I1) AND (NOT I2) AND I3) OR ((NOT I0) AND (NOT I1) AND I2 AND (NOT I3));
  end architecture MUX_4_2;