Decoder in VHDL

Decoder in VHDL

2:4 LINE DECODER (DATA FLOW)

library ieee;
use ieee.std_logic_1164.all;
  entity DEMUX2_4 is
   port(I : in std_logic;
    S0 : in std_logic;
    S1 : in std_logic;
    D0 : out std_logic;
    D1 : out std_logic;
    D2 : out std_logic;
    D3 : out std_logic);
  end entity DEMUX2_4;
  architecture DEMUX_2_4 of DEMUX2_4 is
   begin
    D0<=(NOT S0) AND (NOT S1) AND I;
    D1<= S0 AND (NOT S1) AND I;
    D2<=(NOT S0) AND S1 AND I;
    D3<= S0 AND S1 AND I;
  end architecture DEMUX_2_4;