Demultiplexer in VHDL

Demultiplexer in VHDL

1:2 LINE DEMUX (DATA FLOW)

library ieee;
use ieee.std_logic_1164.all;
  entity DEMUX2 is
   port( S : in std_logic;
    I : in std_logic;
    D0 : out std_logic;
    D1 : out std_logic);
  end entity DEMUX2;
  architecture DEMUX_2 of DEMUX2 is
   begin
    D0<=(NOT S ) AND I;
    D1<= S AND I;
  end architecture DEMUX_2;

1:4 LINE DEMUX (DATA FLOW)

library ieee;
use ieee.std_logic_1164.all;
  entity DEMUX4 is
   port(S0 : in std_logic;
    S1 : in std_logic;
    D0 : out std_logic;
    D1 : out std_logic;
    D2 : out std_logic;
    D3 : out std_logic);
  end entity DEMUX4;
  architecture DEMUX_4 of DEMUX4 is
   begin
    D0<=(NOT S0) AND (NOT S1);
    D1<= S0 AND (NOT S1);
    D2<=(NOT S0) AND S1;
    D3<= S0 AND S1;
  end architecture DEMUX_4;