Binary to Octal Enabled Decoder

Binary to Octal Enabled Decoder

Binary to Octal Enabled Decoder(Behavioural + Data Flow Model)

library ieee;
use ieee.std_logic_1164.all;
 entity ENABLEDECODER3_8 is
  port( A0 : in std_logic;
         A1 : in std_logic;
        A2 : in std_logic;
        En : in std_logic;
        D : out std_logic_vector( 0 to 15));
 end entity ENABLEDECODER3_8;
architecture DECODER_1 of ENABLEDECODER3_8 is
 begin
  process( A0, A1, A2, En)
   -- variable i : INTEGER range 0 to 15;
    begin
     loop1:
      for i in 0 to 15
      loop
       C1: case i is
       when 0=> D(i)<=(NOT A0) AND (NOT A1) AND (NOT A2) AND (NOT En);
       when 1=> D(i)<=A0 AND (NOT A1) AND (NOT A2) AND (NOT En);
       when 2=> D(i)<=(NOT A0) AND A1 AND (NOT A2) AND (NOT En);
       when 3=> D(i)<=A0 AND A1 AND (NOT A2) AND (NOT En);
       when 4=> D(i)<=(NOT A0) AND (NOT A1) AND A2 AND (NOT EN);
       when 5=> D(i)<=A0 AND (NOT A1) AND A2 AND (NOT En);
       when 6=> D(i)<=(NOT A0) AND A1 AND A2 AND (NOT En);
       when 7=> D(i)<=A0 AND A1 AND A2 AND (NOT En);
       when 8=> D(i)<=(NOT A0) AND (NOT A1) AND (NOT A2) AND En;
       when 9=> D(i)<=A0 AND (NOT A1) AND (NOT A2) AND En;
       when 10=> D(i)<=(NOT A0) AND A1 AND (NOT A2) AND En;
       when 11=> D(i)<=A0 AND A1 AND (NOT A2) AND En;
       when 12=> D(i)<=(NOT A0) AND (NOT A1) AND A2 AND En;
       when 13=> D(i)<=A0 AND (NOT A1) AND A2 AND En;
       when 14=> D(i)<=(NOT A0) AND A1 AND A2 AND En;
       when 15=> D(i)<=A0 AND A1 AND A2 AND En;
       end case C1;
      end loop loop1;
  end process;
end architecture DECODER_1;