Binary to Octal Decoder in VHDL

Binary to Octal Decoder in VHDL

Binary to Octal Decoder

library ieee;
use ieee.std_logic_1164.all;
 entity DECOD3_8 is
  port( A0 : in std_logic;
       A1 : in std_logic;
       A2 : in std_logic;
       D0 : out std_logic;
       D1 : out std_logic;
       D2 : out std_logic;
       D3 : out std_logic;
       D4 : out std_logic;
       D5 : out std_logic;
       D6 : out std_logic;
       D7 : out std_logic);
 end entity DECOD3_8;
architecture DECOD_3_8 of DECOD3_8 is
 begin
  D0<= (NOT A0) AND (NOT A1) AND (NOT A2);
  D1<= A0 AND (NOT A1) AND (NOT A2);
  D2<= (NOT A0) AND A1 AND (NOT A2);
  D3<= A0 AND A1 AND (NOT A2);
  D4<= (NOT A0) AND (NOT A1) AND A2;
  D5<= A0 AND (NOT A1) AND A2;
  D6<= (NOT A0) AND A1 AND A2;
  D7<= A0 AND A1 AND A2;
end architecture DECOD_8_3;