8 bit Ripple Carry Adder

8 bit Ripple Carry Adder

8 bit Ripple Carry Adder(Behavioural + Data Flow Model)

library ieee;
use ieee.std_logic_1164.all;
 entity RippleCarry_Adder8 is
   port( Cin : in std_logic;
             Cout : out std_logic;
             A,B : in std_logic_vector(0 to 7);
             Sum : out std_logic_vector( 0 to 7));
 end entity RippleCarry_Adder8;
architecture RippleCarryAdder8 of RippleCarry_Adder8 is
 signal C: std_logic_vector(0 to 8);
   begin
     process(A,B, Cin)
       begin
       C(0)<= Cin;
       loop1:
       for i in 0 to 7
       loop
       C(i+1)<= (A(i) AND B(i)) OR (A(i) AND C(i)) OR (B(i) AND C(i)) ;
       Sum(i)<= A(i) XOR B(i) XOR C(i) ;
       end loop;
       Cout<= C(8);
     end process;
end architecture RippleCarryAdder8;