4 to 3 Priority Encoder in VHDL

4 to 3 Priority Encoder in VHDL

4 to 3 Priority Encoder in VHDL

library ieee;
use ieee.std_logic_1164.all;
 entity PRIO_ENCOD4_3 is
  port( D0 :in std_logic;
       D1 :in std_logic;
       D2 :in std_logic;
       D3 :in std_logic;
       A :out std_logic;
       B :out std_logic;
       V :out std_logic);
 end entity PRIO_ENCOD4_3;
architecture PRIO_ENCOD_4_3 of PRIO_ENCOD4_3 is
 begin
  A<= D2 OR D3;
  B<= ( D1 AND (NOT D2)) OR D3;
  V<= D0 OR D1 OR D2 OR D3;
end architecture PRIO_ENCOD_4_3;